RISC-V ISA
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A RISC-V ISA is an Open-Source Hardware instruction set architecture.
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- Counter-Example(s):
- See: Freeze (Software Engineering), Open-Source Hardware, Reduced Instruction Set Computer.
References
2019
- (Wikipedia, 2019) ⇒ https://en.wikipedia.org/wiki/RISC-V Retrieved:2019-10-7.
- RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.
The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university.
As of June 2019, version 2.2 of the user-space ISA and version 1.11 of the privileged ISA are frozen, permitting software and hardware development to proceed. A debug specification is available as a draft, version 0.3.
- RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.